The present invention relates in general to a staggered finger configuration and more particularly to a staggered finger configuration for chips with staggered bonding pads.
As the efficiency and complexity of semiconductor chips increase, semiconductor packages provide increased efficiency.
In wire bonding, the arrangement of bonding pads on a chip is important. In a package process such as ball grid array (BGA), the pitch of conductive wires on a substrate can be very small due to photolithography technique. Nevertheless, the pitch of the bonding pads is confined by the design rule of wire bonding process, remaining unable to scale down to match the conductive wires. As a result, the arrangement of bonding pads has become a critical parameter in package efficiency.
Generally, the number and pattern of I/O connections between chips and outer circuits depend on the architecture and functions of a chip. Specifically, chips with more functions require more I/O connections.
Conventional bonding pads are arranged singly in-line and staggered. The single in-line arrangement cannot accommodate increased numbers of bonding pads, but the staggered arrangement can improve above fault, as illustrated in FIG. 1 and FIG. 2.
FIG. 1 is a top view of bonding wire connections between a conventional chip with staggered bonding pads and fingers on a substrate. The bonding wire connection comprises a substrate 120, the upper surface of which bear a chip with staggered bonding pads disposed thereon, a plurality of fingers 126a and 126b and a conductive trace 160. A plurality of bonding pads 122a, 122b acting as I/O pads for signals are arranged alternately on the chip 110. Moreover, the bonding pads 122a and 122b connect fingers 126a and 126b by bonding wires 124a and 124b to electrically connect the conductive trace 160. FIG. 2 is a cross-section of FIG. 1 along line 2-2. A package body 150 is formed to encapsulate the chip 110, bonding wires 124a, 124b and the upper surface of the substrate 120 to complete the package 100.
As shown in FIG. 1, the bonding wire 124a connects the outer bonding pad 122a as a signal pad with the finger 126a closer to the chip 110 to electrically connect the conductive trace 160. The bonding wire 124b connects the inner bonding pad 122b as a signal pad with the finger 126b closer to the chip 110 to electrically connect the conductive trace 160. In this case, the number of bonding pads 122a, 122b exceeds the number of fingers 126a, 126b, such that the finger 126a closer to the chip 110 connects to the outer bonding pad 122a, and the finger 126b farthest from the chip 110 connects to the inner bonding pad 122b. As a result, bonding wires are tiered to retain the loop height of the bonding wire 124a lower than that of the bonding wire 124b to prevent shorts in the wire bonding process.
For reduced cost, a common substrate is currently popular in semiconductor chip packaging. With different arrangements of staggered bonding pads on the chip 110, however, it is necessary to rearrange the fingers on the substrate to prevent shorts in the wire bonding process, with more than one arrangements needed. As shown in FIG. 3, the arrangement of bonding pads 122a′, 122b′ is opposite to that in FIG. 1, and the finger 126a′ closer to the chip 110′ connects the inner bonding pad 122a′ and the finger 126b ′ farther from the chip 110 connects the outer bonding pad 122b′, making it different from them to be tiered. As a result, bonding wires 124a′ and 124b′ short easily.
Accordingly, what is needed is a common substrate suitable for a chip with different arrangements of bonding pads to reduce costs and provide more bonding pads on a chip to enhance chip efficiency.